Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.
A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.
Department of Materials Science and Engineering, Yonsei University, 134 Shinchondong, Seoul, 120-749, Korea.
Kyeong-Ju
KJ
Moon
Tae-Il
TI
Lee
Sang-Hoon
SH
Lee
Young-Uk
YU
Han
Moon-Ho
MH
Ham
Jae-Min
JM
Myoung