title: A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.
abstract: We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.
authors.affiliation: School of Electrical Engineering and Computer Science, Seoul National University, Seoul, 151-744, South Korea.
authors.forename: Joo-Young
authors.initials: JY
authors.lastname: Jin
authors.forename: Seung-Hyun
authors.initials: SH
authors.lastname: Yoo
authors.forename: Byung-Wook
authors.initials: BW
authors.lastname: Yoo
authors.forename: Yong-Kweon
authors.initials: YK
authors.lastname: Kim