title: Single InAs/GaSb nanowire low-power CMOS inverter.
abstract: III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.
authors.affiliation: Electrical and Information Technology, Lund University, Lund 221 00, Sweden.
authors.forename: Anil W
authors.initials: AW
authors.lastname: Dey
authors.forename: Johannes
authors.initials: J
authors.lastname: Svensson
authors.forename: B Mattias
authors.initials: BM
authors.lastname: Borg
authors.forename: Martin
authors.initials: M
authors.lastname: Ek
authors.forename: Lars-Erik
authors.initials: LE
authors.lastname: Wernersson