title: Pattern-integrated interference lithography: prospects for nano- and microelectronics.
abstract: In recent years, limitations in optical lithography have challenged the cost-effective manufacture of nano- and microelectronic chips. Spatially regular designs have been introduced to improve manufacturability. However, regular designed layouts typically require an interference step followed by a trim step. These multiple steps increase cost and reduce yield. In the present work, Pattern-Integrated Interference Lithography (PIIL) is introduced to address this problem. PIIL is the integration of interference lithography and superposed pattern mask imaging, combining the interference and the trim into a single-exposure step. Example PIIL implementations and experimental demonstrations are presented. The degrees of freedom associated with the source, pattern mask, and Fourier filter designs are described.
authors.affiliation: School of Electrical and Computer Engineering, Georgia Institute of Technology, 777 Atlantic Drive NW, Atlanta, GA 30332-0250, USA.
authors.forename: Matthieu C R
authors.initials: MC
authors.lastname: Leibovici
authors.forename: Guy M
authors.initials: GM
authors.lastname: Burrow
authors.forename: Thomas K
authors.initials: TK
authors.lastname: Gaylord
mesh_terms: D004581:Electronics / Q000295:instrumentation*; D007368:Interferometry / Q000379:methods*; D054802:Molecular Imprinting / Q000379:methods*; D053758:Nanoparticles / Q000737:chemistry*; D036103:Nanotechnology / Q000295:instrumentation*; D010781:Photography / Q000379:methods*; D013499:Surface Properties; D018511:Systems Integration