title: Three-dimensional etching of silicon for the fabrication of low-dimensional and suspended devices.
abstract: In order to expand the use of nanoscaled silicon structures we present a new etching method that allows us to shape silicon with sub-10 nm precision. This top-down, CMOS compatible etching scheme allows us to fabricate silicon devices with quantum behavior without relying on difficult lateral lithography. We utilize this novel etching process to create quantum dots, quantum wires, vertical transistors and ultra-high-aspect ratio structures. We believe that this etching technique will have broad and significant impacts and applications in nano-photonics, bio-sensing, and nano-electronics.
authors.affiliation: California Institute of Technology, 1200 E. California Blvd., MC 200-36, Pasadena, CA 91125, USA. walavalk@caltech.edu
authors.forename: Sameer S
authors.initials: SS
authors.lastname: Walavalkar
authors.forename: Andrew P
authors.initials: AP
authors.lastname: Homyk
authors.forename: M David
authors.initials: MD
authors.lastname: Henry
authors.forename: Axel
authors.initials: A
authors.lastname: Scherer
mesh_terms: D003460:Crystallization / Q000379:methods*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008422:Materials Testing; D008968:Molecular Conformation; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure*; D010316:Particle Size; D045663:Quantum Dots; D012825:Silicon / Q000737:chemistry*; D013499:Surface Properties; D014173:Transistors, Electronic
chemical_list: D012825:Silicon