Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.
Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.
DSP/IC Design Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan. djchen@video.ee.ntu.edu.tw
Tung-Chien
TC
Chen
Tsung-Chuan
TC
Ma
Yun-Yu
YY
Chen
Liang-Gee
LG
Chen
D000200:Action Potentials / Q000502:physiology*; D000465:Algorithms; D000818:Animals; D001921:Brain / Q000502:physiology*; D011211:Electric Power Supplies; D004569:Electroencephalography / Q000295:instrumentation*; D006801:Humans; D008838:Microcomputers; D010363:Pattern Recognition, Automated / Q000379:methods*; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D014173:Transistors, Electronic