title: Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects.
abstract: We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k = 2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.
authors: School of Integrative Engineering, Chung-Ang University, Seoul 156-756, Korea.
authors: Sung Gyu
authors: SG
authors: Pyo
authors: Soo Won
authors: SW
authors: Kim
mesh_terms: D003300:Copper / Q000737:chemistry*; D003460:Crystallization / Q000379:methods*; D004553:Electric Conductivity; D046911:Macromolecular Substances / Q000737:chemistry; D008422:Materials Testing; D053768:Metal Nanoparticles / Q000737:chemistry* / Q000648:ultrastructure*; D008968:Molecular Conformation; D010316:Particle Size; D016062:Porosity; D013499:Surface Properties
chemical_list: D046911:Macromolecular Substances; D003300:Copper