title: Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2gate stacks.
abstract: The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2high-kdielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOzinterfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011eV-1cm-2are demonstrated. The formation of the high-kLaxGeyOzlayer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
authors.affiliation: Integrated Devices and Circuits, KTH Royal Institute of Technology, School of ICT, Stockholm, Sweden.
authors.forename: Christoph
authors.initials: C
authors.lastname: Henkel
authors.forename: Per-Erik
authors.initials: PE
authors.lastname: Hellström
authors.forename: Mikael
authors.initials: M
authors.lastname: Ostling
authors.forename: Michael
authors.initials: M
authors.lastname: Stöger-Pollach
authors.forename: Ole
authors.initials: O
authors.lastname: Bethge
authors.forename: Emmerich
authors.initials: E
authors.lastname: Bertagnolli
keywords: Annealing; Germanate; Germanium; High-k; La2O3; Oxidation; ZrO2