title: Low-temperature performance of accumulation-mode p-channel wrap-gated FinFETs.
abstract: In this work, accumulation-mode (AM) p-channel wrap-gated FinFETs and AM p-channel planar FETs are fabricated using top-down strategies, and compared in performance at temperatures from 6 K to 295 K. The threshold voltage variation of the AM wrap-gated FinFET is slightly larger than that of the AM planar FET. The drain current and the peak transconductance in the AM wrap-gated FinFET are larger than those in the AM planar FET, and those differences are temperature dependent. We attribute those to the body current enhancement in the AM wrap-gated FinFET as temperature increases. The subthreshold swings (SS) of both types of the FETs improve with temperature decreasing and get lower than 10 mV/dec at 6 K. The higher SS in the AM wrap-gated FinFET is likely due to a high interface state density at the fin sidewalls arising from the fin patterning induced defects.
authors: Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
authors: Yanbo
authors: Y
authors: Zhang
authors: Yandong
authors: Y
authors: Du
authors: Yankun
authors: Y
authors: Chen
authors: Xiaoming
authors: X
authors: Lil
authors: Xiang
authors: X
authors: Yang
authors: Weihua
authors: W
authors: Han
authors: Fuhua
authors: F
authors: Yang