title: Dimensional optimization of nanowire--complementary metal oxide--semiconductor inverter.
abstract: This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.
authors: Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, University Science Malaysia, 14300 Nibong Tebal, Penang, Malaysia.
authors: Yasir
authors: Y
authors: Hashim
authors: Othman
authors: O
authors: Sidek
mesh_terms: D017076:Computer-Aided Design; D004553:Electric Conductivity; D004867:Equipment Design; D019544:Equipment Failure Analysis; D008670:Metals / Q000737:chemistry*; D049329:Nanostructures / Q000737:chemistry* / Q000648:ultrastructure; D010087:Oxides / Q000737:chemistry; D012666:Semiconductors; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D014173:Transistors, Electronic
chemical_list: D008670:Metals; D010087:Oxides