title: Energy-efficient neuron, synapse and STDP integrated circuits.
abstract: Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.
authors.affiliation: Microelectronics Laboratory, HRL Laboratories LLC, Malibu, CA 90265 USA. jcruz@hrl.com
authors.forename: Jose M
authors.initials: JM
authors.lastname: Cruz-Albrecht
authors.forename: Michael W
authors.initials: MW
authors.lastname: Yung
authors.forename: Narayan
authors.initials: N
authors.lastname: Srinivasa
mesh_terms: D001698:Biomedical Engineering; D001921:Brain / Q000502:physiology; D003201:Computers; D004567:Electrodes, Implanted; D004581:Electronics; D004867:Equipment Design; D006801:Humans; D008959:Models, Neurological; D016571:Neural Networks, Computer; D009474:Neurons / Q000502:physiology*; D019736:Prostheses and Implants; D012815:Signal Processing, Computer-Assisted; D013569:Synapses / Q000502:physiology*; D009435:Synaptic Transmission / Q000502:physiology