title: Design of efficient full adder in quantum-dot cellular automata.
abstract: Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μ m(2)) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.
authors.affiliation: Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India. bibhash.sen@gmail.com
authors.forename: Bibhash
authors.initials: B
authors.lastname: Sen
authors.forename: Ayush
authors.initials: A
authors.lastname: Rajoria
authors.forename: Biplab K
authors.initials: BK
authors.lastname: Sikdar
mesh_terms: D039301:Computers, Molecular; D004867:Equipment Design; D019544:Equipment Failure Analysis; D036103:Nanotechnology / Q000295:instrumentation*; D045663:Quantum Dots; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*