title: Design of silicon brains in the nano-CMOS era: spiking neurons, learning synapses and neural architecture optimization.
abstract: We present a design framework for neuromorphic architectures in the nano-CMOS era. Our approach to the design of spiking neurons and STDP learning circuits relies on parallel computational structures where neurons are abstracted as digital arithmetic logic units and communication processors. Using this approach, we have developed arrays of silicon neurons that scale to millions of neurons in a single state-of-the-art Field Programmable Gate Array (FPGA). We demonstrate the validity of the design methodology through the implementation of cortical development in a circuit of spiking neurons, STDP synapses, and neural architecture optimization.
authors.affiliation: Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218, USA. andrewca@us.ibm.com
authors.forename: Andrew S
authors.initials: AS
authors.lastname: Cassidy
authors.forename: Julius
authors.initials: J
authors.lastname: Georgiou
authors.forename: Andreas G
authors.initials: AG
authors.lastname: Andreou
mesh_terms: D000200:Action Potentials / Q000502:physiology*; D001921:Brain / Q000166:cytology* / Q000502:physiology; D003198:Computer Simulation; D006801:Humans; D007858:Learning; D008959:Models, Neurological; D009474:Neurons / Q000502:physiology*
keywords: FPGA neural arrays; Learning in silicon; Neuromorphic engineering; Silicon brains; Silicon neurons