title: Clock recovery PLL with gated PFD for NRZ ON-OFF Modulated Signals in a retinal implant system.
abstract: A Clock Recovery Phase Locked Loop with Gated Phase Frequency Detector (GPLL) for NRZ ON-OFF Modulated Signals with low data transmission rates for an inductively powered subretinal implant system is presented. Low data transmission rate leads to a long absence of inductive powering in the system when zeros are transmitted. Consequently there is no possibility to extract any clock in these pauses, thus the digital circuitry can not work any more. Compared to a commonly used PLL for clock extraction, no certain amount of data transitions is needed. This is achieved by having two operating modes. In one mode the GPLL tracks the HF input signal. In the other, the GPLL is an adjustable oscillator oscillating at the last used frequency. The proposed GPLL is fabricated and measured using a 350 nm High Voltage CMOS technology.
authors.forename: Christian
authors.initials: C
authors.lastname: Brendler
authors.forename: Naser Pour
authors.initials: NP
authors.lastname: Aryan
authors.forename: Viola
authors.initials: V
authors.lastname: Rieger
authors.forename: Albrecht
authors.initials: A
authors.lastname: Rothermel
mesh_terms: D004582:Electronics, Medical / Q000295:instrumentation*; D004867:Equipment Design; D005246:Feedback; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D057488:Visual Prosthesis