title: Combining instruction prefetching with partial cache locking to improve WCET in real-time systems.
abstract: Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.
authors.affiliation: School of Computer Science and Engineering, Beihang University, Beijing, China.
authors.forename: Fan
authors.initials: F
authors.lastname: Ni
authors.affiliation: School of Computer Science and Engineering, Beihang University, Beijing, China.
authors.forename: Xiang
authors.initials: X
authors.lastname: Long
authors.affiliation: School of Computer Science and Engineering, Beihang University, Beijing, China.
authors.forename: Han
authors.initials: H
authors.lastname: Wan
authors.affiliation: School of Computer Science and Engineering, Beihang University, Beijing, China.
authors.forename: Xiaopeng
authors.initials: X
authors.lastname: Gao
mesh_terms: D000465:Algorithms; D003201:Computers; D012984:Software