Stego on FPGA: an IWT approach.
A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).
School of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, India.
Balakrishnan
B
Ramalingam
School of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, India.
Rengarajan
0000-0003-1574-3045
R
Amirtharajan
School of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, India.
John Bosco Balaguru
0000-0003-4641-9870
JB
Rayappan
D000465:Algorithms; D016494:Computer Security / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D016247:Information Storage and Retrieval / Q000379:methods*; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D058067:Wavelet Analysis