SELF ALIGNED TIP DEINSULATION OF ATOMIC LAYER DEPOSITED AL2O3AND PARYLENE C COATED UTAH ELECTRODE ARRAY BASED NEURAL INTERFACES.
The recently developed alumina and Parylene C bi-layer encapsulation improved the lifetime of neural interfaces. Tip deinsulation of Utah electrode array based neural interfaces is challenging due to the complex 3D geometries and high aspect ratios of the devices. A three-step self-aligned process was developed for tip deinsulation of bilayer encapsulated arrays. The deinsulation process utilizes laser ablation to remove Parylene C, O2reactive ion etching to remove carbon and Parylene residues, and buffered oxide etch to remove alumina deposited by atomic layer deposition, and expose the IrOxtip metallization. The deinsulated iridium oxide area was characterized by scanning electron microscopy, atomic force microscopy, X-ray photoelectron spectroscopy, and electrochemical impedance spectroscopy to determine the morphology, surface morphology, composition, and electrical properties of the deposited layers and deinsulated tips. The alumina layer was found to prevent the formation of micro cracks on iridium oxide during the laser ablation process, which has been previously reported as a challenge for laser deinsulation of Parylene films. The charge injection capacity, charge storage capacity, and impedance of deinsulated iridium oxide were characterized to determine the deinsulation efficacy compared to Parylene-only insulation. Deinsulated iridium oxide with bilayer encapsulation had higher charge injection capacity (240 vs 320 nC) and similar electrochemical impedance (2.5 vs 2.5 kΩ) compared to deinsulated iridium oxide with only Parylene coating for an area of 2 × 10-4cm2. Tip impedances were in the ranges of 20 to 50 kΩ, with median of 32 KΩ and standard deviation of 30 kΩ, showing the effectiveness of the self-aligned deinsulation process for alumina and Parylene C bi-layer encapsulation. The relatively uniform tip impedance values demonstrated the consistency of tip exposures.
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA.
Xianzong
X
Xie
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA.
Loren
L
Rieth
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA.
Sandeep
S
Negi
Blackrock Microsystems, Salt Lake City, Utah 84108 USA.
Rajmohan
R
Bhandari
Department of Bioengineering, University of Utah, Salt Lake City, UT 84112 USA.
Ryan
R
Caldwell
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA.
Rohit
R
Sharma
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA.
Prashant
P
Tathireddy
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112 USA ; Department of Bioengineering, University of Utah, Salt Lake City, UT 84112 USA.
Florian
F
Solzbacher