Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.
This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.
College of Communication Engineering, Chongqing University (CQU), Shapingba, Chongging 400044, China.
Fang
0000-0003-2453-4878
F
Tang
Hong Kong University of Science and Technology (HKUST), ECE Department, Clear Water Bay, Kowloon, Hong Kong.
Amine
A
Bermak
School of Computing, University of West Scotland, Paisley, Renfrewshire, UK.
Amira
A
Abbes
Qatar University, 2713 Doha, Qatar.
Mohieddine Amor
MA
Benammar
D000465:Algorithms; D008962:Models, Theoretical