title: Neural CMOS-integrated circuit and its application to data classification.
abstract: Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.
authors.forename: Izzet Cem
authors.initials: IC
authors.lastname: Göknar
authors.forename: Merih
authors.initials: M
authors.lastname: Yildiz
authors.forename: Shahram
authors.initials: S
authors.lastname: Minaei
authors.forename: Engin
authors.initials: E
authors.lastname: Deniz
mesh_terms: D000465:Algorithms; D016002:Discriminant Analysis; D004867:Equipment Design; D019544:Equipment Failure Analysis; D016571:Neural Networks, Computer; D010363:Pattern Recognition, Automated / Q000379:methods*; D012666:Semiconductors; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*