title: Graphene/Si CMOS hybrid hall integrated circuits.
abstract: Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Le
authors.initials: L
authors.lastname: Huang
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Huilong
authors.initials: H
authors.lastname: Xu
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Zhiyong
authors.initials: Z
authors.lastname: Zhang
authors.affiliation: ASIC and System Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China.
authors.forename: Chengying
authors.initials: C
authors.lastname: Chen
authors.affiliation: ASIC and System Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China.
authors.forename: Jianhua
authors.initials: J
authors.lastname: Jiang
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Xiaomeng
authors.initials: X
authors.lastname: Ma
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Bingyan
authors.initials: B
authors.lastname: Chen
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Zishen
authors.initials: Z
authors.lastname: Li
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Hua
authors.initials: H
authors.lastname: Zhong
authors.affiliation: Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
authors.forename: Lian-Mao
authors.initials: LM
authors.lastname: Peng