title: Germanium avalanche receiver for low power interconnects.
abstract: Recent advances in silicon photonics have aided the development of on-chip communications. Power consumption, however, remains an issue in almost all integrated devices. Here, we report a 10 Gbit per second waveguide avalanche germanium photodiode under low reverse bias. The avalanche photodiode scheme requires only simple technological steps that are fully compatible with complementary metal oxide semiconductor processes and do not need nanometre accuracy and/or complex epitaxial growth schemes. An intrinsic gain higher than 20 was demonstrated under a bias voltage as low as -7 V. The Q-factor relating to the signal-to-noise ratio at 10 Gbit per second was maintained over 20 dB without the use of a trans-impedance amplifier for an input optical power lower than -26 dBm thanks to an aggressive shrinkage of the germanium multiplication region. A maximum gain over 140 was also obtained for optical powers below -35 dBm. These results pave the way for low-power-consumption on-chip communication applications.
authors.affiliation: 1] Institut d'Electronique Fondamentale (IEF), Université Paris-Sud, CNRS, Bât 220, F-91405 Orsay, France [2] CEA, LETI, Minatec Campus, 17 rue des Martyrs, F-38054 Grenoble, France [3] STMicroelectronics, Silicon Technology Development, Crolles, France.
authors.forename: Léopold
authors.initials: L
authors.lastname: Virot
authors.affiliation: Institut d'Electronique Fondamentale (IEF), Université Paris-Sud, CNRS, Bât 220, F-91405 Orsay, France.
authors.forename: Paul
authors.initials: P
authors.lastname: Crozat
authors.affiliation: CEA, LETI, Minatec Campus, 17 rue des Martyrs, F-38054 Grenoble, France.
authors.forename: Jean-Marc
authors.initials: JM
authors.lastname: Fédéli
authors.affiliation: CEA, LETI, Minatec Campus, 17 rue des Martyrs, F-38054 Grenoble, France.
authors.forename: Jean-Michel
authors.initials: JM
authors.lastname: Hartmann
authors.affiliation: Institut d'Electronique Fondamentale (IEF), Université Paris-Sud, CNRS, Bât 220, F-91405 Orsay, France.
authors.forename: Delphine
authors.initials: D
authors.lastname: Marris-Morini
authors.affiliation: Institut d'Electronique Fondamentale (IEF), Université Paris-Sud, CNRS, Bât 220, F-91405 Orsay, France.
authors.forename: Eric
authors.initials: E
authors.lastname: Cassan
authors.affiliation: STMicroelectronics, Silicon Technology Development, Crolles, France.
authors.forename: Frédéric
authors.initials: F
authors.lastname: Boeuf
authors.affiliation: Institut d'Electronique Fondamentale (IEF), Université Paris-Sud, CNRS, Bât 220, F-91405 Orsay, France.
authors.forename: Laurent
authors.initials: L
authors.lastname: Vivien