title: Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps.
abstract: In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state (D it). The variability of the off-state current (I off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D it varying from 5 × 10(12) to 5 × 10(13) eV(-1) cm(-2) owing to significant threshold voltage (V th) fluctuation. The results of this study indicate that if the level of D it is lower than 1 × 10(12) eV(-1) cm(-2), the normalized variability of the on-state current, I off, V th, DIBL, and subthreshold swing is within 5%.
authors.affiliation: Parallel and Scientific Computing Laboratory, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan ; Institute of Communications Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan.
authors.forename: Sheng-Chia
authors.initials: SC
authors.lastname: Hsu
authors.affiliation: Parallel and Scientific Computing Laboratory, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan ; Institute of Communications Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan ; Department of Electrical and Computer Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan.
authors.forename: Yiming
authors.initials: Y
authors.lastname: Li
keywords: Bulk FinFETs; Density of interface traps; Electrical characteristic fluctuation; Interface trap fluctuation; Random interface traps; Statistical device simulation