title: Break-before-make CMOS inverter for power-efficient delay implementation.
abstract: A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.
authors.affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.
authors.forename: Janez
authors.identifier: 0000-0003-3288-8254
authors.initials: J
authors.lastname: Puhan
authors.affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.
authors.forename: Dušan
authors.initials: D
authors.lastname: Raič
authors.affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.
authors.forename: Tadej
authors.identifier: 0000-0001-6030-0820
authors.initials: T
authors.lastname: Tuma
authors.affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.
authors.forename: Árpád
authors.identifier: 0000-0002-3035-1376
authors.initials: Á
authors.lastname: Bűrmen
mesh_terms: D008962:Models, Theoretical; D014173:Transistors, Electronic