title: A scalable FPGA-based cerebellum for passage-of-time representation.
abstract: The cerebellum plays a critical role for sensorimotor control and learning. However dysmertria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. To foster a potential cure based on neuroprosthetic technology, we present a frame-based Network-on-Chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with 100,000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The results demonstrate that our implementation can reproduce the POT functionality properly. The computational speed can achieve to 25.6 ms for simulating 1 sec real world activities. Furthermore, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical applications.
authors.forename: Junwen
authors.initials: J
authors.lastname: Luo
authors.forename: Graeme
authors.initials: G
authors.lastname: Coapes
authors.forename: Terrence
authors.initials: T
authors.lastname: Mak
authors.forename: Tadashi
authors.initials: T
authors.lastname: Yamazaki
authors.forename: Chung
authors.initials: C
authors.lastname: Tin
authors.forename: Patrick
authors.initials: P
authors.lastname: Degenaar
mesh_terms: D000818:Animals; D001185:Artificial Intelligence; D002531:Cerebellum / Q000502:physiology*; D004581:Electronics; D008954:Models, Biological; D016571:Neural Networks, Computer; D013997:Time Factors