title: A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.
abstract: This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.
authors.forename: Yi-Xiao
authors.initials: YX
authors.lastname: Wang
authors.forename: Wei-Ming
authors.initials: WM
authors.lastname: Chen
authors.forename: Chung-Yu
authors.initials: CY
authors.lastname: Wu
mesh_terms: D011211:Electric Power Supplies; D004582:Electronics, Medical / Q000295:instrumentation*; D019736:Prostheses and Implants