Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging.
We present the design, operation, and test results of a new time interval/delay generator that provides the resolution of 0.3 ps, jitter below 10 ps (rms), and wide delay range of 10 s. The wide range has been achieved by counting periods of a reference clock while the high resolution and low jitter have been obtained through the two-time use of inner interpolation. This interpolation, based on charging of a single capacitor, provides both the precise external trigger synchronization and accurate generation of residual time interval. A combination of both processes virtually eliminates triggering indeterminacy. The jitter between the trigger and output is below 1 ps, which ensures a high performance delay. The generator is integrated in a single application specific integrated circuit chip using a standard cost-effective 0.35 μm CMOS process.
Military University of Technology, Kaliskiego 2, 00-908 Warsaw, Poland.
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K
Klepacki
Military University of Technology, Kaliskiego 2, 00-908 Warsaw, Poland.
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M
Pawłowski
Military University of Technology, Kaliskiego 2, 00-908 Warsaw, Poland.
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R
Szplet