title: Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.
abstract: This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS.
authors.forename: Jun Yeon
authors.initials: JY
authors.lastname: Won
authors.forename: Sun Il
authors.initials: SI
authors.lastname: Kwon
authors.forename: Hyun Suk
authors.initials: HS
authors.lastname: Yoon
authors.forename: Guen Bae
authors.initials: GB
authors.lastname: Ko
authors.forename: Jeong-Whan
authors.initials: JW
authors.lastname: Son
authors.forename: Jae Sung
authors.initials: JS
authors.lastname: Lee
mesh_terms: D000703:Analog-Digital Conversion; D002138:Calibration / Q000592:standards; D004867:Equipment Design / Q000592:standards*; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D013995:Time