title: Scaling of graphene integrated circuits.
abstract: The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.
authors: L-NESS, Department of Physics, Politecnico di Milano, Polo di Como, Via Anzani 42, 22100 Como, Italy. roman.sordan@polimi.it.
authors: Massimiliano
authors: M
authors: Bianchi
authors: Erica
authors: E
authors: Guerriero
authors: Marco
authors: M
authors: Fiocco
authors: Ruggero
authors: R
authors: Alberti
authors: Laura
authors: L
authors: Polloni
authors: Ashkan
authors: A
authors: Behnam
authors: Enrique A
authors: EA
authors: Carrion
authors: Eric
authors: E
authors: Pop
authors: Roman
authors: R
authors: Sordan