title: NULL convention floating point multiplier.
abstract: Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.
authors: Centre for Research, Anna University, Chennai, Tamilnadu 600025, India.
authors: Anitha Juliette
authors: 0000-0002-0365-737X
authors: AJ
authors: Albert
authors: Faculty of Information and Communication Engineering, College of Engineering, Anna University, Chennai, Tamilnadu 600025, India.
authors: Seshasayanan
authors: S
authors: Ramachandran