title: A closed-loop compressive-sensing-based neural recording system.
abstract: OBJECTIVE
  This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device.
  
  
  METHODS
  The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases.
  
  
  RESULTS
  Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode.
  
  
  CONCLUSIONS
  Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.
authors: Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, USA.
authors: Jie
authors: J
authors: Zhang
authors: Srinjoy
authors: S
authors: Mitra
authors: Yuanming
authors: Y
authors: Suo
authors: Andrew
authors: A
authors: Cheng
authors: Tao
authors: T
authors: Xiong
authors: Frederic
authors: F
authors: Michon
authors: Marleen
authors: M
authors: Welkenhuysen
authors: Fabian
authors: F
authors: Kloosterman
authors: Peter S
authors: PS
authors: Chin
authors: Steven
authors: S
authors: Hsiao
authors: Trac D
authors: TD
authors: Tran
authors: Firat
authors: F
authors: Yazicioglu
authors: Ralph
authors: R
authors: Etienne-Cummings
mesh_terms: D000465:Algorithms; D000703:Analog-Digital Conversion; D000818:Animals; D001921:Brain / Q000502:physiology*; D044962:Data Compression / Q000379:methods*; D011211:Electric Power Supplies; D004569:Electroencephalography / Q000295:instrumentation*; D004867:Equipment Design; D019544:Equipment Failure Analysis; D005246:Feedback; D051381:Rats; D015203:Reproducibility of Results; D012680:Sensitivity and Specificity; D012815:Signal Processing, Computer-Assisted / Q000295:instrumentation*; D059629:Signal-To-Noise Ratio