InAs/Si Hetero-Junction Nanotube Tunnel Transistors.
Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in 'ON' state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.
Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical and Mathematical Sciences &Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia.
Amir N
AN
Hanna
Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical and Mathematical Sciences &Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia.
Hossain M
HM
Fahad
Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical and Mathematical Sciences &Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia.
Muhammad M
MM
Hussain