title: Nanoscale Buckling of Ultrathin Low-k Dielectric Lines during Hard-Mask Patterning.
abstract: Commonly known in macroscale mechanics, buckling phenomena are now also encountered in the nanoscale world as revealed in today's cutting-edge fabrication of microelectronics. The description of nanoscale buckling requires precise dimensional and elastic moduli measurements, as well as a thorough understanding of the relationships between stresses in the system and the ensuing morphologies. Here, we analyze quantitatively the buckling mechanics of organosilicate fins that are capped with hard masks in the process of lithographic formation of deep interconnects. We propose an analytical model that quantitatively describes the morphologies of the buckled fins generated by residual stresses in the hard mask. Using measurements of mechanical properties and geometric characteristics, we have verified the predictions of the analytical model for structures with various degrees of buckling, thus putting forth a framework for guiding the design of future nanoscale interconnect architectures.
authors.affiliation: †Material Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899, United States.|‡Department of Mechanical Engineering, University of Maryland, College Park, Maryland 20742, United States.
authors.forename: Gheorghe
authors.initials: G
authors.lastname: Stan
authors.affiliation: §Department of Mechanical Engineering, Colorado School of Mines, Golden, Colorado 80401, United States.
authors.forename: Cristian V
authors.initials: CV
authors.lastname: Ciobanu
authors.affiliation: †Material Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899, United States.
authors.forename: Igor
authors.initials: I
authors.lastname: Levin
authors.affiliation: ∥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Hui J
authors.initials: HJ
authors.lastname: Yoo
authors.affiliation: ∥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Alan
authors.initials: A
authors.lastname: Myers
authors.affiliation: ∥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Kanwal
authors.initials: K
authors.lastname: Singh
authors.affiliation: ∥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Christopher
authors.initials: C
authors.lastname: Jezewski
authors.affiliation: ⊥Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Barbara
authors.initials: B
authors.lastname: Miner
authors.affiliation: ⊥Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, United States.
authors.forename: Sean W
authors.initials: SW
authors.lastname: King
keywords: interconnect circuits; low-k dielectric patterns; nanoscale buckling