title: Silicon interposer BGA package with a Cu-filled through silicon via and a multilayer redistribution layer fabricated via electroplating.
abstract: As large-scale integrated circuit chips become smaller, conventional organic buildup substrates can no longer support them. To resolve this problem, silicon interposers with through silicon via (TSV) technology are gaining recognition as alternative solution to provide high-density interconnection, improved electrical performance due to shorter interconnection from the die to substrate for nano-scale devices. In this study, we fabricated a silicon interposer to achieve high density and high performance packages. Via holes were etched via the Bosch process using a deep reactive ion etcher and SiO2 formed with a diffusion furnace as the diffusion barrier of the Cu electrode. TSVs were filled with Cu under various electroplating conditions. After Cu filling, a Cu post was formed directly using the over-filled Cu electrode through a chemical mechanical polishing process. A double-layer redistribution layer was formed on one side of the interposer using a lift-off process. Sn-3.5% Ag solder bumps 40 μm in diameter were formed directly on the Cu post on another side of the interposer using electroplating and the reflow method.
authors.forename: Taeyoo
authors.initials: T
authors.lastname: Kim
authors.forename: Hwajin
authors.initials: H
authors.lastname: Son
authors.forename: Seung-Kyu
authors.initials: SK
authors.lastname: Lim
authors.forename: Yongil
authors.initials: Y
authors.lastname: Song
authors.forename: Sujeong
authors.initials: S
authors.lastname: Suh