title: Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.
abstract: This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
authors.affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.
authors.forename: Ya-Chi
authors.initials: YC
authors.lastname: Cheng
authors.forename: Hung-Bin
authors.initials: HB
authors.lastname: Chen
authors.forename: Jun-Ji
authors.initials: JJ
authors.lastname: Su
authors.forename: Chi-Shen
authors.initials: CS
authors.lastname: Shao
authors.forename: Cheng-Ping
authors.initials: CP
authors.lastname: Wang
authors.forename: Chun-Yen
authors.initials: CY
authors.lastname: Chang
authors.forename: Yung-Chun
authors.initials: YC
authors.lastname: Wu