title: The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility.
abstract: The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm(2) at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 10(8), subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm(2)/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics.
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Wen
authors.initials: W
authors.lastname: Yang
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Qing-Qing
authors.initials: QQ
authors.lastname: Sun
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Yang
authors.initials: Y
authors.lastname: Geng
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Lin
authors.initials: L
authors.lastname: Chen
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Peng
authors.initials: P
authors.lastname: Zhou
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: Shi-Jin
authors.initials: SJ
authors.lastname: Ding
authors.affiliation: 1] Collaborative Innovation Center of IC Design and Manufacturing of Yangtze River Delta [2] Institute of Advanced Nanodevices, School of Microelectronics, Fudan University, Shanghai 200433, China.
authors.forename: David Wei
authors.initials: DW
authors.lastname: Zhang