title: Efficient Implementation of a Symbol Timing Estimator for Broadband PLC.
abstract: Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA.
authors: Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, Spain. francisco.nombela@depeca.uah.es.
authors: Francisco
authors: F
authors: Nombela
authors: Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, Spain. enrique.garcia@depeca.uah.es.
authors: Enrique
authors: E
authors: García
authors: Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, Spain. raul@depeca.uah.es.
authors: Raúl
authors: R
authors: Mateos
authors: Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, Spain. alvaro.hernandez@uah.es.
authors: Álvaro
authors: Á
authors: Hernández
keywords: FPGA-based architecture; Power-Line Communications; Zadoff-Chu sequences; complementary sequences; symbol timing estimation