title: A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction.
abstract: This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures.
authors.affiliation: Institute of Microelectronics, Tsinghua University, Beijing 100084, China. jglwiz@gmail.com.
authors.forename: Guangli
authors.initials: G
authors.lastname: Jiang
authors.affiliation: Institute of Microelectronics, Tsinghua University, Beijing 100084, China. liulb@tsinghua.edu.cn.
authors.forename: Leibo
authors.initials: L
authors.lastname: Liu
authors.affiliation: Institute of Microelectronics, Tsinghua University, Beijing 100084, China. zhuwp08@mails.tsinghua.edu.cn.
authors.forename: Wenping
authors.initials: W
authors.lastname: Zhu
authors.affiliation: Institute of Microelectronics, Tsinghua University, Beijing 100084, China. yinsy@tsinghua.edu.cn.
authors.forename: Shouyi
authors.initials: S
authors.lastname: Yin
authors.affiliation: Institute of Microelectronics, Tsinghua University, Beijing 100084, China. wsj@tsinghua.edu.cn.
authors.forename: Shaojun
authors.initials: S
authors.lastname: Wei
keywords: AKAZE; VLSI implementation; binary feature descriptor; feature extraction; hardware architecture