title: Current-limiting challenges for all-spin logic devices.
abstract: All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications.
authors.affiliation: Fert Beijing Institute, Univ. Beihang, 100191, Beijing, China.|School of Electrical &Information Engineering, Beihang Univ, Beijing 100191, Peoples R China.|Institut d'Electronique Fondamentale, Univ. Paris-Sud, F-91405 Orsay, France.|UMR 8622, CNRS, F-91405 Orsay, France.
authors.forename: Li
authors.initials: L
authors.lastname: Su
authors.affiliation: Fert Beijing Institute, Univ. Beihang, 100191, Beijing, China.|School of Electrical &Information Engineering, Beihang Univ, Beijing 100191, Peoples R China.
authors.forename: Youguang
authors.initials: Y
authors.lastname: Zhang
authors.affiliation: Institut d'Electronique Fondamentale, Univ. Paris-Sud, F-91405 Orsay, France.|UMR 8622, CNRS, F-91405 Orsay, France.
authors.forename: Jacques-Olivier
authors.initials: JO
authors.lastname: Klein
authors.affiliation: Fert Beijing Institute, Univ. Beihang, 100191, Beijing, China.|School of Electrical &Information Engineering, Beihang Univ, Beijing 100191, Peoples R China.
authors.forename: Yue
authors.initials: Y
authors.lastname: Zhang
authors.affiliation: Institut d'Electronique Fondamentale, Univ. Paris-Sud, F-91405 Orsay, France.|UMR 8622, CNRS, F-91405 Orsay, France.
authors.forename: Arnaud
authors.initials: A
authors.lastname: Bournel
authors.affiliation: Fert Beijing Institute, Univ. Beihang, 100191, Beijing, China.|School of Electrical &Information Engineering, Beihang Univ, Beijing 100191, Peoples R China.|Unité Mixte de Physique CNRS-Thales, F-91767 Palaiseau, France.
authors.forename: Albert
authors.initials: A
authors.lastname: Fert
authors.affiliation: Fert Beijing Institute, Univ. Beihang, 100191, Beijing, China.|School of Electrical &Information Engineering, Beihang Univ, Beijing 100191, Peoples R China.|Institut d'Electronique Fondamentale, Univ. Paris-Sud, F-91405 Orsay, France.|UMR 8622, CNRS, F-91405 Orsay, France.
authors.forename: Weisheng
authors.initials: W
authors.lastname: Zhao