title: Vertically Integrated Multiple Nanowire Field Effect Transistor.
abstract: A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.|Department of Memory Business, Samsung Electronics , San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 445-701, Republic of Korea.
authors.forename: Byung-Hyun
authors.initials: BH
authors.lastname: Lee
authors.affiliation: Department of Nano-process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Min-Ho
authors.initials: MH
authors.lastname: Kang
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Dae-Chul
authors.initials: DC
authors.lastname: Ahn
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Jun-Young
authors.initials: JY
authors.lastname: Park
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Tewook
authors.initials: T
authors.lastname: Bang
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Seung-Bae
authors.initials: SB
authors.lastname: Jeon
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Jae
authors.initials: J
authors.lastname: Hur
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Dongil
authors.initials: D
authors.lastname: Lee
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Yang-Kyu
authors.initials: YK
authors.lastname: Choi
keywords: field-effect transistor (FET); gate-all-around (GAA); one-route all-dry etch; silicon nanowire (SiNW); three-dimensional nonvolatile memory; vertical integration