title: III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.
abstract: III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.
authors.affiliation: Electrical and Information Technology, Lund University , Box 118, 221 00 Lund, Sweden.
authors.forename: Johannes
authors.initials: J
authors.lastname: Svensson
authors.affiliation: Electrical and Information Technology, Lund University , Box 118, 221 00 Lund, Sweden.
authors.forename: Anil W
authors.initials: AW
authors.lastname: Dey
authors.affiliation: Solid State Physics/The Nanometer Structure Consortium, Lund University , Box 118, 221 00 Lund, Sweden.
authors.forename: Daniel
authors.initials: D
authors.lastname: Jacobsson
authors.affiliation: Electrical and Information Technology, Lund University , Box 118, 221 00 Lund, Sweden.
authors.forename: Lars-Erik
authors.initials: LE
authors.lastname: Wernersson
keywords: CMOS; GaSb; III−V; InAs; NAND; Si; inverter; low-power logic; nanowire