title: Performance Evaluation and Implementation of FPGA Based SGSF in Smart Diagnostic Applications.
abstract: The main objective of the paper is to implement Savitzky Golay Smoothing Filter (SGSF) so as to apply in pre-processing of real time smart medical diagnostic systems. As very important information of EEG and ECG waveforms lies in the peak of the signal, hence it becomes absolutely necessary to filter noise and artifacts from the signal. The implemented filter should be able to reject the noise efficiently along with the least distortion from the original signal. The shape preserving characteristics of the filter are determined by introducing different noise levels in the signal. The designed filter is tested on synthetic signals of EEG and ECG by adding different types of noise and the performance is analysed on various parameters, i.e., SNR, SSNR, SNRI, MSE, COR and signal distortion of the final output. The smoothing performance comparison of SGSF with the most commonly used Moving Average Filter (MAF) proves that SGSF is more efficient. Hence it is suggested that MAF can be replaced by SGSF. For real time issues, it is further implemented on reconfigurable architectures so as to achieve high speed, low cost, low power consumption and less area. Therefore SGSF is realized on FPGA platform to combine the advantages of both. Real time EEG and ECG signals are also considered for experimentation. The experimental results show that the proposed methodology (FPGA-SGSF) significantly reduces the processing time and preserves the actual features of the signal.
authors.affiliation: Instrumentation and Control Engineering Division, NSIT, University of Delhi, Sec-3 Dwarka, New Delhi, India. agarwal.shivangi@gmail.com.
authors.forename: Shivangi
authors.initials: S
authors.lastname: Agarwal
authors.affiliation: Instrumentation and Control Engineering Division, NSIT, University of Delhi, Sec-3 Dwarka, New Delhi, India. ashansit@gmail.com.
authors.forename: Asha
authors.initials: A
authors.lastname: Rani
authors.affiliation: Instrumentation and Control Engineering Division, NSIT, University of Delhi, Sec-3 Dwarka, New Delhi, India. vijaydee@gmail.com.
authors.forename: Vijander
authors.initials: V
authors.lastname: Singh
authors.affiliation: Instrumentation and Control Engineering Division, NSIT, University of Delhi, Sec-3 Dwarka, New Delhi, India. mittalap@gmail.com.
authors.forename: A P
authors.initials: AP
authors.lastname: Mittal
mesh_terms: D000465:Algorithms; D003199:Computer Systems; D004562:Electrocardiography / Q000379:methods*; D004569:Electroencephalography / Q000379:methods*; D006801:Humans; D015203:Reproducibility of Results; D012815:Signal Processing, Computer-Assisted
keywords: COR (correlation coefficient); FPGA based Savitzky Golay Smoothing Filter (FPGA-SGSF); Field Programmable Gate Array (FPGA); SNRI (SNR improvement); SSNR (Signal-to-signal-plus-noise ratio)