title: A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.
abstract: This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.
authors.affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea. gimmingyu@hanyang.ac.kr.
authors.forename: Min-Kyu
authors.initials: MK
authors.lastname: Kim
authors.affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea. seongkhong@hanyang.ac.kr.
authors.forename: Seong-Kwan
authors.initials: SK
authors.lastname: Hong
authors.affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea. okwon@hanyang.ac.kr.
authors.forename: Oh-Kyong
authors.initials: OK
authors.lastname: Kwon
keywords: CMOS image sensor; column parallel readout; successive approximation register ADC