title: Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model.
abstract: Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes' toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
authors: Electronics and Communications Department, Faculty of Engineering, Cairo University, University Street, P.O. Box 268, Giza 12316, Egypt.
authors: Omnia S
authors: OS
authors: Fadl
authors: Electronics and Communications Department, Faculty of Engineering, Cairo University, University Street, P.O. Box 268, Giza 12316, Egypt.
authors: Mohamed F
authors: MF
authors: Abu-Elyazeed
authors: College of Computing and Information Technology (CCIT), AASTMT, P.O. Box 2033, El Moshir Ismail st., Heliopolis, Cairo, Egypt.
authors: Mohamed B
authors: MB
authors: Abdelhalim
authors: Electronics and Communications Engineering Department, American University in Cairo, P.O. Box 74, New Cairo 11835, Egypt.
authors: Hassanein H
authors: HH
authors: Amer
authors: Radiation Engineering Department, NCRRT, 3 Ahmed El Zomor St., P.O. Box 29, Cairo 11787, Egypt.
authors: Ahmed H
authors: AH
authors: Madian
keywords: CMOS combinational logic circuits; Dynamic power estimation; Logic pictures; Real-delay model; Switching activity; Toggle rate