title: A Vertically Integrated Junctionless Nanowire Transistor.
abstract: A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.|Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, 18448, Republic of Korea.
authors.forename: Byung-Hyun
authors.initials: BH
authors.lastname: Lee
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Jae
authors.initials: J
authors.lastname: Hur
authors.affiliation: Department of Nano-process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Min-Ho
authors.initials: MH
authors.lastname: Kang
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Tewook
authors.initials: T
authors.lastname: Bang
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Dae-Chul
authors.initials: DC
authors.lastname: Ahn
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Dongil
authors.initials: D
authors.lastname: Lee
authors.affiliation: Department of Nano-process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Kwang-Hee
authors.initials: KH
authors.lastname: Kim
authors.affiliation: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors.forename: Yang-Kyu
authors.initials: YK
authors.lastname: Choi
keywords: Silicon nanowire (SiNW); gate-all-around (GAA); junctionless transistor; one-route all-dry etch; three-dimensional nonvolatile memory; vertical integration