title: A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.
abstract: This paper presents a 4 × VDDneuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.
authors.forename: Zhicong
authors.initials: Z
authors.lastname: Luo
authors.forename: Ming-Dou
authors.initials: MD
authors.lastname: Ker
mesh_terms: D000818:Animals; D004558:Electric Stimulation; D004560:Electricity; D004567:Electrodes, Implanted; D004569:Electroencephalography / Q000295:instrumentation / Q000379:methods; D004867:Equipment Design; D006801:Humans; D009474:Neurons / Q000502:physiology*; D051381:Rats; D020318:Rats, Long-Evans; D012666:Semiconductors