Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thicknesses.
This paper presents a combined physical and electrical post-fabrication method for determining the thicknesses of the various layers in a commercial 1.5 μm complementary-metal-oxide-semiconductor (CMOS) foundry process available through MOSIS. Forty-two thickness values are obtained from physical step-height measurements performed on thickness test structures and from electrical measurements of capacitances, sheet resistances, and resistivities. Appropriate expressions, numeric values, and uncertainties for each layer of thickness are presented, along with a systematic nomenclature for interconnect and dielectric thicknesses. However, apparent inconsistencies between several of the physical and electrical results for film thickness suggest that further uncertainty analysis is required and the effects of several assumptions need to be quantified.
National Institute of Standards and Technology, Gaithersburg, MD 20899-8120.
Janet C
JC
Marshall
University of Southern California, Marina del Rey, CA 90292.
P Thomas
PT
Vernier
CMOS; MEMS; Young’s modulus; nomenclature; platform height; step height; test structures; thickness