title: Embedded Implementation of VHR Satellite Image Segmentation.
abstract: Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance. Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc. In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage.
authors.affiliation: Laboratory LE2I UMR 6306, CNRS, Arts et M&#233;tiers, University Bourgogne Franche-Comt&#233;, 21000 Dijon, France. chao.li.1986@ieee.org.
authors.forename: Chao
authors.initials: C
authors.lastname: Li
authors.affiliation: Laboratory LE2I UMR 6306, CNRS, Arts et M&#233;tiers, University Bourgogne Franche-Comt&#233;, 21000 Dijon, France. balla_arabe_souleymane@ieee.org.
authors.forename: Souleymane
authors.initials: S
authors.lastname: Balla-Arabé
authors.affiliation: Laboratory LE2I UMR 6306, CNRS, Arts et M&#233;tiers, University Bourgogne Franche-Comt&#233;, 21000 Dijon, France. dom@le2i.cnrs.fr.
authors.forename: Dominique
authors.initials: D
authors.lastname: Ginhac
authors.affiliation: Laboratory LE2I UMR 6306, CNRS, Arts et M&#233;tiers, University Bourgogne Franche-Comt&#233;, 21000 Dijon, France. fanyang@u-bourgogne.fr.
authors.forename: Fan
authors.initials: F
authors.lastname: Yang
keywords: FPGA; SW/HW co-design; active contour model; embedded system; high performance computing; high-level synthesis; image segmentation; lattice Boltzmann method; level set method; remote sensing