title: Valley-engineered ultra-thin silicon for high-performance junctionless transistors.
abstract: Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.
authors.affiliation: School of Electrical Engineering, KAIST, Daejeon, 305-701 Korea.
authors.forename: Seung-Yoon
authors.initials: SY
authors.lastname: Kim
authors.affiliation: School of Electrical Engineering, KAIST, Daejeon, 305-701 Korea.
authors.forename: Sung-Yool
authors.initials: SY
authors.lastname: Choi
authors.affiliation: Department of Materials Engineering, Korea Aerospace University, Gyeonggi-do, 412-791, Korea.
authors.forename: Wan Sik
authors.initials: WS
authors.lastname: Hwang
authors.affiliation: School of Electrical Engineering, KAIST, Daejeon, 305-701 Korea.
authors.forename: Byung Jin
authors.initials: BJ
authors.lastname: Cho