title: Vertically Integrated Nanowire-Based Unified Memory.
abstract: A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.
authors: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.|Department of Memory Business, Samsung Electronics , San 16 Banwol-Dong, Hwasung City, Gyeonggi-Do 18448, Republic of Korea.
authors: Byung-Hyun
authors: BH
authors: Lee
authors: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors: Dae-Chul
authors: DC
authors: Ahn
authors: Department of Nano-Process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors: Min-Ho
authors: MH
authors: Kang
authors: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors: Seung-Bae
authors: SB
authors: Jeon
authors: School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
authors: Yang-Kyu
authors: YK
authors: Choi
keywords: 1T-DRAM; NAND flash memory; Vertically integrated nanowire; one-route all-dry etching process; unified memory; zRAM