title: Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors.
abstract: In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade-1) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.
authors.affiliation: Low Power Nanoelectronics Research Group, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Simrol 453552, India.
authors.forename: Manish
authors.initials: M
authors.lastname: Gupta
authors.forename: Abhinav
authors.initials: A
authors.lastname: Kranti