title: Efficient BinDCT hardware architecture exploration and implementation on FPGA.
abstract: This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.
authors.affiliation: Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia; High Institute of Informatics and Mathematics of Monastir, Monastir, Tunisia.
authors.forename: Abdessalem
authors.initials: A
authors.lastname: Ben Abdelali
authors.affiliation: Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia.
authors.forename: Ichraf
authors.initials: I
authors.lastname: Chatti
authors.affiliation: Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia; Institut Jean Lamour (IJL) UMR7198, University of Lorraine, Vandoeuvre Les Nancy, France.
authors.forename: Marwa
authors.initials: M
authors.lastname: Hannachi
authors.affiliation: Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia.
authors.forename: Abdellatif
authors.initials: A
authors.lastname: Mtibaa
keywords: Binary discrete cosine transform; Design exploration; Discrete cosine transform approximation; Field programmable gate array; Hardware implementation; Very large scale integration architectures