title: Fabrication of sub-10 nm metal nanowire arrays with sub-1 nm critical dimension control.
abstract: Sub-10 nm metal nanowire arrays are important electrodes for building high density emerging 'beyond CMOS' devices. We made Pt nanowire arrays with sub-10 nm feature size using nanoimprint lithography on silicon substrates with 100 nm thick thermal oxide. We further studied the critical dimension (CD) evolution in the fabrication procedure and achieved 0.4 nm CD control, providing a viable solution to the imprint lithography CD challenge as specified by the international technology roadmap for semiconductors. Finally, we fabricated Pt/TiO2/Pt memristor crossbar arrays with the 8 nm electrodes, demonstrating great potential in dimension scaling of this emerging device.
authors.affiliation: Nanodevices and Integrated Systems Laboratory, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA.
authors.forename: Shuang
authors.initials: S
authors.lastname: Pi
authors.forename: Peng
authors.initials: P
authors.lastname: Lin
authors.forename: Qiangfei
authors.initials: Q
authors.lastname: Xia