The MasPar MP-1 As a Computer Arithmetic Laboratory.
This paper is a blueprint for the use of a massively parallel SIMD computer architecture for the simulation of various forms of computer arithmetic. The particular system used is a DEC/MasPar MP-1 with 4096 processors in a square array. This architecture has many advantages for such simulations due largely to the simplicity of the individual processors. Arithmetic operations can be spread across the processor array to simulate a hardware chip. Alternatively they may be performed on individual processors to allow simulation of a massively parallel implementation of the arithmetic. Compromises between these extremes permit speed-area tradeoffs to be examined. The paper includes a description of the architecture and its features. It then summarizes some of the arithmetic systems which have been, or are to be, implemented. The implementation of the level-index and symmetric level-index, LI and SLI, systems is described in some detail. An extensive bibliography is included.
Cray Research Inc., Calverton, MD 20705.
Michael A
MA
Anuta
National Institute of Standards and Technology, Gaithersburg, MD 20899-0001.
Daniel W
DW
Lozier
United States Naval Academy, Annapolis, MD 21402.
Peter R
PR
Turner
computer arithmetic; fixed-point and floating-point arithmetic; logarithmic and level-index arithmetic; residue number system arithmetic; serial and parallel simulation of computer arithmetic