title: Digital hardware implementation of a stochastic two-dimensional neuron model.
abstract: This study explores the feasibility of stochastic neuron simulation in digital systems (FPGA), which realizes an implementation of a two-dimensional neuron model. The stochasticity is added by a source of current noise in the silicon neuron using an Ornstein-Uhlenbeck process. This approach uses digital computation to emulate individual neuron behavior using fixed point arithmetic operation. The neuron model's computations are performed in arithmetic pipelines. It was designed in VHDL language and simulated prior to mapping in the FPGA. The experimental results confirmed the validity of the developed stochastic FPGA implementation, which makes the implementation of the silicon neuron more biologically plausible for future hybrid experiments.
authors.affiliation: LTI Lab., University of Picardie Jules Verne, France; IMS Lab., University of Bordeaux, France. Electronic address: filippo.grassia@u-picardie.fr.
authors.forename: F
authors.initials: F
authors.lastname: Grassia
authors.affiliation: LIMMS/CNRS-IIS, Institute of Industrial Science, The University of Tokyo, Japan.
authors.forename: T
authors.initials: T
authors.lastname: Kohno
authors.affiliation: IMS Lab., University of Bordeaux, France; LIMMS/CNRS-IIS, Institute of Industrial Science, The University of Tokyo, Japan.
authors.forename: T
authors.initials: T
authors.lastname: Levi
mesh_terms: D003198:Computer Simulation; D003201:Computers; D008959:Models, Neurological; D009474:Neurons / Q000502:physiology*
keywords: FPGA silicon neuron; Neuromorphic engineering; Noise; Spiking neuron model; Stochastic neuron