title: The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.
abstract: Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.
authors.affiliation: Samsung Electronics, Hwaseong-si, Gyeonggi-do 18448, Korea. seungho.ok@samsung.com.
authors.forename: Seung-Ho
authors.initials: SH
authors.lastname: Ok
authors.affiliation: School of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Korea. yhlee@kumoh.ac.kr.
authors.forename: Yong-Hwan
authors.initials: YH
authors.lastname: Lee
authors.affiliation: School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea. jhshim@knu.ac.kr.
authors.forename: Jae Hoon
authors.initials: JH
authors.lastname: Shim
authors.affiliation: School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA. limsk@ece.gatech.edu.
authors.forename: Sung Kyu
authors.initials: SK
authors.lastname: Lim
authors.affiliation: School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea. bihmoon@knu.ac.kr.
authors.forename: Byungin
authors.initials: B
authors.lastname: Moon
keywords: low-power; stereo matching processor; technology scaling; through-silicon via