title: An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks.
abstract: In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced within silicomodeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of anin silicospiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments.
authors.affiliation: EOLab - Microelectronics and Bioengineering Lab, Department of Electrical and Electronic Engineering, University of Cagliari Cagliari, Italy.
authors.forename: Danilo
authors.initials: D
authors.lastname: Pani
authors.affiliation: EOLab - Microelectronics and Bioengineering Lab, Department of Electrical and Electronic Engineering, University of Cagliari Cagliari, Italy.
authors.forename: Paolo
authors.initials: P
authors.lastname: Meloni
authors.affiliation: EOLab - Microelectronics and Bioengineering Lab, Department of Electrical and Electronic Engineering, University of Cagliari Cagliari, Italy.
authors.forename: Giuseppe
authors.initials: G
authors.lastname: Tuveri
authors.affiliation: Information Engineering Unit, PolComIng Department, University of Sassari Sassari, Italy.
authors.forename: Francesca
authors.initials: F
authors.lastname: Palumbo
authors.affiliation: Neuroengineering and Bio-nano Technology Lab, Dibris, University of Genova Genova, Italy.
authors.forename: Paolo
authors.initials: P
authors.lastname: Massobrio
authors.affiliation: EOLab - Microelectronics and Bioengineering Lab, Department of Electrical and Electronic Engineering, University of Cagliari Cagliari, Italy.
authors.forename: Luigi
authors.initials: L
authors.lastname: Raffo
keywords: FPGA; closed-loop hardware accelerator; fixed-point; neural simulator; real-time