Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device.
We report on the mitigation of curtaining artifacts during transmission electron microscopy (TEM) lamella preparation by means of a modified ion beam milling approach, which involves altering the incident angle of the Ga ions by rocking of the sample on a special stage. We applied this technique to TEM sample preparation of a state-of-the-art integrated circuit based on a 14-nm technology node. Site-specific lamellae with a thickness <15 nm were prepared by top-down Ga focused ion beam polishing through upper metal contacts. The lamellae were analyzed by means of high-resolution TEM, which showed a clear transistor structure and confirmed minimal curtaining artifacts. The results are compared with a standard inverted thinning preparation technique.
1TESCAN ORSAY HOLDING,Libušina třída 21,62300 Brno,Czech Republic.
Andrey
A
Denisyuk
2TESCAN Brno,Libušina třída 1,62300 Brno,Czech Republic.
Tomáš
T
Hrnčíř
1TESCAN ORSAY HOLDING,Libušina třída 21,62300 Brno,Czech Republic.
Jozef
J
Vincenc Oboňa
2TESCAN Brno,Libušina třída 1,62300 Brno,Czech Republic.
Sharang
2TESCAN Brno,Libušina třída 1,62300 Brno,Czech Republic.
Martin
M
Petrenec
1TESCAN ORSAY HOLDING,Libušina třída 21,62300 Brno,Czech Republic.
Jan
J
Michalička
FinFET device; TEM sample; integrated circuit; lamella